1. Field of the Invention
The present invention relates to the reduction of power consumption in a microelectronic system integrated onto a single chip.
2. Description of the Related Art Referring to FIG. 1, a single-chip system 10 of this type conventionally comprises a central processing unit (CPU) 11, a read-only memory (ROM) 12, a random-access memory (RAM) 13, a serial input-output interface (SIO) 14, a clock divider (DIV) 15, and various on-chip peripheral circuits (not shown).
The CPU 11 carries out prescribed computations and control processing according to a program stored in the chip's memory (the ROM 12 and/or RAM 13). The ROM 12 is a nonvolatile memory that retains its data even after power is switched off. Programs stored in the ROM 12 include a bootstrap program or initial program loader (IPL), interrupt handlers that handle external interrupts, and other programs. The RAM 13 is a volatile memory that loses its data when power is switched off. The RAM 13 is used to store application programs and data being processed.
The serial input-output interface 14 is used to transfer data between the CPU 11 and an external device (in this case, an external memory device 30 such as a flash memory). The serial input-output interface 14 converts parallel data received from the CPU 11 to serial data and sends the data to the external device, and converts serial data received from the external device to parallel data and supplies the data to the CPU 11. The clock divider 15 divides the frequency (for example, 10 MHz) of a system clock SCK received from an external source to obtain a high-speed clock signal CKH (with a frequency of, for example, 5 MHz), which is supplied to the CPU 11, and a low-speed clock signal CKL (with a frequency of, for example, 1 MHz), which is supplied to the serial input-output interface 14 and used for serial data transfer.
The operation of this integrated circuit during transitions between its normal mode and a power-saving mode will now be described.
When the CPU 11 has finished executing a series of processes and is ready to power down into the power-saving mode, the CPU 11 reads out the data stored in the RAM 13 and supplies the data one byte at a time to the serial input-output interface 14. The serial input-output interface 14 converts the data received from the CPU 11 to serial data synchronized with the low-speed clock signal CKL and transfers the data to the external memory device 30. When one byte of data has been transferred, the serial input-output interface 14 sends a transfer completion signal DON to the CPU 11. The CPU 11 then supplies the next byte of data to the serial input-output interface 14. When all the, necessary data have been transferred to the external memory device 30, the CPU 11 powers off prescribed circuits, including the RAM 13, and goes into the power-saving mode. Even in this power-saving mode, the CPU 11, ROM 12, and clock divider 15 remain powered so that they can detect an external interrupt INT and execute a transition from the power-saving mode to the normal mode.
Upon detection of an external interrupt INT in the power-saving mode, the CPU 11 powers up the circuits that were powered off, operating according to a program stored in the ROM 12. The CPU 11 then sends a byte data read command to the serial input-output interface 14. The serial input-output interface 14 retrieves one byte of data from the external memory device 30 in response to the instruction, and sends a transfer completion signal DON to the CPU 11. The CPU 11 stores the retrieved data in the RAM 13. The CPU 11 continues to issue data read commands to the serial input-output interface 14 until all necessary data have been stored in the RAM 13. When the necessary data have been stored in the RAM 13, the CPU 11 resumes normal operation.
A microelectronic system in which a uniform transmission speed is maintained between the microelectronic system and peripheral units even when the clock frequency is changed to conserve power is described in Japanese Patent Application Publication No. 8-234865.
A problem with the integrated circuit described above is that during the transitions between the normal mode and the power-saving mode, while data are being transferred between the serial input-output interface 14 and the external memory device 30 in synchronization with the low-speed clock signal CKL supplied to the serial input-output interface 14, the CPU 11 continues to receive the high-speed clock signal CKH. The CPU 11 therefore operates on a clock signal with a higher speed than necessary, consuming power needlessly.
Moreover, the CPU 11 has to wait for an external interrupt INT and carry out a transition from the power-saving mode to the normal mode, so the high-speed clock signal CKH cannot be halted, limiting the reduction of power consumption.